CD00161566 Datasheet, PDF (12/105 Pages) STMicroelectronics – nullMedium-density performance line ARM-based 32-bit MCU

Description
STM32F103x8, STM32F103xB
Figure 2. Clock tree
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
MCO
8 MHz
HSI RC
HSI
/2
PLLSRC _PLLMUL
..., x16
x2, x3, x4
PLL
FLITFCLK
to Flash programming interface
USB
Prescaler
48 MHz
USBCLK
to USB interface
/1, 1.5
72 MHz max
HCLK
to AHB bus, core,
Clock
memory and DMA
SW
Enable (3 bits)
/8
to Cortex System timer
FCLK Cortex
HSI
PLLCLK
HSE
SYSCLK AHB
72 MHz ^Prescaler
max ^{/1, 2..512}
APB1
Prescaler
/1, 2, 4, 8, 16
free running clock
36 MHz max
PCLK1
to APB1
Peripheral Clock ^peripherals
Enable (13 bits)
CSS
TIM2,3, 4
to TIM2, 3
and 4
If (APB1 prescaler =1) x1
TIMXCLK
else
x2 _{Peripheral Clock}
Enable (3 bits)
4-16 MHz
HSE OSC
PLLXTPRE
/2
LSE OSC
32.768 kHz
/128
LSE
to RTC
RTCCLK
APB2
Prescaler
/1, 2, 4, 8, 16
72 MHz max
PCLK2
to APB2
Peripheral Clock ^peripherals
Enable (11 bits)
TIM1 timer
to TIM1
If (APB2 prescaler =1) x1
TIM1CLK
else
x2 _{Peripheral Clock}
ADC
Prescaler
/2, 4, 6, 8
Enable (1 bit)
to ADC
ADCCLK
RTCSEL[1:0]
LSI RC
40 kHz
LSI
to Independent Watchdog (IWDG)
IWDGCLK
Main
/2
Clock Output
MCO
PLLCLK
HSI
HSE
SYSCLK
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
ai14903
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48
MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
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DocID13587 Rev 16