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CD00161566 Datasheet, PDF (62/105 Pages) STMicroelectronics – nullMedium-density performance line ARM-based 32-bit MCU
◁
Electrical characteristics
STM32F103x8, STM32F103xB
5.3.13 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.
Table 35. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO
input low level
-
voltage
VIL Low level input voltage IO FT(3) input
low level voltage
-
- 0.28*(VDD-2 V)+0.8 V(1)
- 0.32*(VDD-2V)+0.75 V(1)
All I/Os except
BOOT0
-
-
0.35VDD(2)
Standard IO
V
input high level 0.41*(VDD-2 V)+1.3 V(1) -
-
voltage
VIH
High level input
voltage
IO FT(3) input
high level
0.42*(VDD-2 V)+1 V(1) -
-
voltage
All I/Os except
BOOT0
0.65VDD(2)
-
-
Standard IO Schmitt
Vhys
trigger voltage
hysteresis(4)
IO FT Schmitt trigger
voltage hysteresis(4)
200
-
5% VDD(5)
-
-
mV
-
VSS  VIN  VDD
Ilkg
Input leakage current
(6)
Standard I/Os
VIN = 5 V
I/O FT
-
-
-
1
µA
-
3
RPU
Weak pull-up
equivalent resistor(7)
RPD
Weak pull-down
equivalent resistor(7)
VIN VSS
VIN VDD
30
40
50
k
30
40
50
CIO I/O pin capacitance
-
5
-
pF
1. Data based on design simulation.
2. Tested in production.
3.
FT = Five-volt
disabled.
tolerant.
In
order
to
sustain
a
voltage
higher
than
VDD+0.3
the
internal
pull-up/pull-down
resistors
must
be
4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
5. With a minimum of 100 mV.
6. Leakage could be higher than max. if negative current is injected on adjacent pins.
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