CD00161566 Datasheet, PDF (72/105 Pages) STMicroelectronics – nullMedium-density performance line ARM-based 32-bit MCU

Electrical characteristics
STM32F103x8, STM32F103xB
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under the ambient temperature, f_PCLKx frequency and V_DD supply voltage
conditions summarized in Table 9.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 42. SPI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
f_SCK
1/t_c(SCK)
SPI clock frequency
Master mode
Slave mode
-
18
MHz
-
18
t_r(SCK)
t_f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
DuCy(SCK)
SPI slave input
duty cycle
clock
Slave mode
t_su(NSS)(1) NSS setup time
Slave mode
t_h(NSS)(1) NSS hold time
Slave mode
tt_{ww((SSCCKKHL))((11))}
SCK high and low time
Master mode, f_PCLK = 36 MHz,
presc = 4
tt_{ssuu((MSII))((11))}
Data input setup time
Master mode
Slave mode
t_h(MI) ⁽¹⁾
t_h(SI)(1)
Data input hold time
Master mode
Slave mode
t_a(SO)(1)(2)
Data output access
time
Slave mode, f_PCLK = 20 MHz
-
8
ns
30
70
%
4t_PCLK
-
2t_PCLK
-
50
60
5
-
5
-
5
-
4
-
ns
0
3t_PCLK
t_{dis(SO)(1)(3)}
Data output disable
time
Slave mode
2
10
t_v(SO) ⁽¹⁾ Data output valid time Slave mode (after enable edge)
25
t_v(MO)(1) Data output valid time Master mode (after enable edge)
5
t_h(SO)(1)
t_h(MO)(1)
Data output hold time
Slave mode (after enable edge)
Master mode (after enable edge)
15
2
-
-
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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