CD00161566 Datasheet, PDF (70/105 Pages) STMicroelectronics – nullMedium-density performance line ARM-based 32-bit MCU

Electrical characteristics
STM32F103x8, STM32F103xB
5.3.16
Communications interfaces
I²C interface characteristics
The STM32F103xx performance line I²C interface meets the requirements of the standard
I²C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V_DD is disabled, but is still present.
The I²C characteristics are described in Table 40. Refer also to Section 5.3.12: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Symbol
Table 40. I²C characteristics
Parameter
Standard mode I²C⁽¹⁾
Min
Max
Fast mode I²C⁽¹⁾⁽²⁾
Min
Max
Unit
t_w(SCLL)
t_w(SCLH)
t_su(SDA)
t_h(SDA)
t_r(SDA)
t_r(SCL)
t_f(SDA)
t_f(SCL)
t_h(STA)
t_su(STA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
4.7
-
4.0
-
250
-
0
-
1.3
-
µs
0.6
100
-
0
900⁽³⁾
-
1000 20 + 0.1C_b
300
ns
-
300
-
300
4.0
-
0.6
-
µs
4.7
-
0.6
-
t_su(STO) Stop condition setup time
4.0
-
0.6
-
s
t_w(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
s
C_b
Capacitive load for each bus
line
-
400
-
400
pF
1. Guaranteed by design, not tested in production.
2.
af^Pc^Ch^Li^Ke¹vemfuasstt
be at least 2 MHz to achieve standard mode I²C frequencies. It
mode I²C frequencies. It must be a multiple of 10 MHz to reach
must be
the 400
at least 4 MHz
kHz maximum
to
I2C
fast mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
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