C8051F50X Datasheet, PDF (98/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
12.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F50x-F51x devices implement 64 kB or
32 kB of this program memory space as in-system, re-programmable Flash memory, organized in a contig-
uous block from addresses 0x0000 to 0xFFFF in 64 kB devices and addresses 0x0000 to 0x7FFF in 32 kB
devices. The address 0xFBFF in 64 kB devices and 0x7FFF in 32 kB devices serves as the security lock
byte for the device. Addresses above 0xFDFF are reserved in the 64 kB devices.
C8051F500/1/2/3/8/9
Reserved Area
Lock Byte
Lock Byte Page
0xFFFF
0xFC00
0xFBFF
0xFBFE
0xFA00
Flash Memory Space
(64kB Flash Device)
C8051F504/5/6/7-F510/1
Lock Byte
Lock Byte Page
Flash Memory Space
(32kB Flash Device)
0x7FFF
0x7FFE
0x7E00
0x0000
Figure 12.2. Flash Program Memory Map
0x0000
12.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F50x-F51x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to
read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the C8051F50x-F51x to update program code and use the program
memory space for non-volatile data storage. Refer to Section “15. Flash Memory” on page 129 for further
details.
12.2. Data Memory
The C8051F50x-F51x devices include 4352 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. The other 4096 bytes of this memory is on-chip “exter-
nal” memory. The data memory map is shown in Figure 12.1 for reference.
12.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
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Rev. 1.1