C8051F50X Datasheet, PDF (214/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
LIN Register Definition 21.7. LIN0ERR: LIN0 Error Register
Bit
7
6
5
4
3
2
1
0
Name
SYNCH PRTY
TOUT
CHK BITERR
Type
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Indirect Address = 0x0A
Bit
Name
Function
7:5 Unused Read = 000b; Write = Don’t Care
4
SYNCH Synchronization Error Bit (slave mode only).
0: No error with the SYNCH FIELD has been detected.
1: Edges of the SYNCH FIELD are outside of the maximum tolerance.
3
PRTY Parity Error Bit (slave mode only).
0: No parity error has been detected.
1: A parity error has been detected.
2
TOUT Timeout Error Bit.
0: A timeout error has not been detected.
1: A timeout error has been detected. This error is detected whenever one of the fol-
lowing conditions is met:
• The master is expecting data from a slave and the slave does not respond.
• The slave is expecting data but no data is transmitted on the bus.
• A frame is not finished within the maximum frame length.
• The application does not set the DTACK bit (LIN0CTRL.4) or STOP bit
(LIN0CTRL.7) until the end of the reception of the first byte after the identifier.
1
CHK
Checksum Error Bit.
0: Checksum error has not been detected.
1: Checksum error has been detected.
0
BITERR Bit Transmission Error Bit.
0: No error in transmission has been detected.
1: The bit value monitored during transmission is different than the bit value sent.
214
Rev. 1.1