C8051F50X Datasheet, PDF (179/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
20.1.3. Interfacing Port I/O in a Multi-Voltage System
All Port I/O are capable of interfacing to digital logic operating at a supply voltage higher than VDD and
less than 5.25 V. Connect the VIO pin to the voltage source of the interface logic.
20.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P3.7 can be assigned to various analog, digital, and external interrupt functions. P4.0-
P4.7 can be assigned to only digital functions. The Port pins assigned to analog functions should be con-
figured for analog I/O, and Port pins assigned to digital or external interrupt functions should be configured
for digital I/O.
20.2.1. Assigning Port I/O Pins to Analog Functions
Table 20.1 shows all available analog functions that require Port I/O assignments. Port pins selected for
these analog functions should have their corresponding bit in PnSKIP set to 1. This reserves the pin
for use by the analog function and does not allow it to be claimed by the Crossbar. Table 20.1 shows the
potential mapping of Port I/O to each analog function.
Table 20.1. Port I/O Assignment for Analog Functions
Analog Function
ADC Input
Comparator0 or Compartor1 Input
Potentially Assignable
Port Pins
P0.0–P3.7*
P0.0–P2.7
Voltage Reference (VREF0)
P0.0
External Oscillator in Crystal Mode (XTAL1)
P0.2
External Oscillator in RC, C, or Crystal Mode (XTAL2)
P0.3
*Note: P3.1–P3.7 are only available on the 48-pin and 40-pin packages
SFR(s) used for
Assignment
ADC0MX, PnSKIP
CPT0MX, CPT1MX,
PnSKIP
REF0CN, PnSKIP
OSCXCN, PnSKIP
OSCXCN, PnSKIP
20.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 20.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Table 20.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
SFR(s) used for
Assignment
UART0, SPI0, SMBus,
Any Port pin available for assignment by the
CAN0, LIN0, CP0, CP0A, Crossbar. This includes P0.0–P4.7* pins which
CP1, CP1A, SYSCLK, PCA0 have their PnSKIP bit set to 0.
(CEX0-5 and ECI), T0 or T1. Note: The Crossbar will always assign UART0 pins
to P0.4 and P0.5 and always assign CAN0 to
P0.6 and P0.7.
XBR0, XBR1, XBR2
Any pin used for GPIO
P0.0–P4.7*
P0SKIP, P1SKIP,
P2SKIP, P3SKIP
*Note: P3.1–P3.7 and P4.0 are only available on the 48-pin and 40pin packages. P4.1–P4.7 are only available on
the 48-pin package. A skip register is not available for P4.
Rev. 1.1
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