C8051F50X Datasheet, PDF (102/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
0x0
(SPI0DAT)
SFR Page
Stack SFR's
SFRPAGE
SFRNEXT
SFRLAST
Figure 13.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT
While CIP-51 executes in-line code (writing values to SPI0DAT in this example), the CAN0 Interrupt
occurs. The CIP-51 vectors to the CAN0 ISR and pushes the current SFR Page value (SFR Page 0x00)
into SFRNEXT in the SFR Page Stack. The SFR page needed to access CAN’s SFRs is then automatically
placed in the SFRPAGE register (SFR Page 0x0C). SFRPAGE is considered the “top” of the SFR Page
Stack. Software can now access the CAN0 SFRs. Software may switch to any SFR Page by writing a new
value to the SFRPAGE register at any time during the CAN0 ISR to access SFRs that are not on SFR
Page 0x0C. See Figure 13.3.
102
Rev. 1.1