C8051F50X Datasheet, PDF (76/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “20.3. Priority Crossbar Decoder” on
page 180 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V_DD) + 0.25 V without damage or upset. The complete Comparator elec-
trical specifications are given in Table 5.12.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 9.2). Selecting a longer response time reduces the Comparator supply current. See Table X for com-
plete timing and supply current requirements.
CPn+
VIN+
VIN- ^CPn-
+
CPn
_
OUT
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CPnHYP Bits)
VIN-
INPUTS
VIN+
Negative Hysteresis Voltage
(Programmed by CPnHYN Bits)
VOH
OUTPUT
VOL
Positive Hysteresis
Disabled
Negative Hysteresis
Disabled
Maximum
Positive Hysteresis
Maximum
Negative Hysteresis
Figure 9.2. Comparator Hysteresis Plot
Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN.
The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in
Figure 9.2, various levels of negative hysteresis can be programmed, or negative hysteresis can be dis-
abled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see Section “9.3. Interrupt Handler” on page 91.) The CPnFIF flag is set to
1 upon a Comparator falling-edge, and the CPnRIF flag is set to 1 upon the Comparator rising-edge. Once
set, these bits remain set until cleared by software. The output state of the Comparator can be obtained at
any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to 1, and is dis-
abled by clearing this bit to 0.
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