C8051F50X Datasheet, PDF (56/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
Note: When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
System Clock
Convert Start
P o s t-T ra c k in g
AD0TM = 01
AD0EN = 0
D ual-Tracking
AD0TM = 11
AD0EN = 0
P o w ere d
Down
P o w er-U p
and Idle
TC TC TC TC
P o w ere d
Down
P o w er-U p
and Track
TC TC TC TC
AD0PWR
P ow e re d
Down
P ow e re d
Down
P o w e r-U p
and Idle
T C..
P o w e r-U p
and Track
T C..
P o s t-T ra c k in g
AD0TM = 01
AD0EN = 1
D ual-Tracking
AD0TM = 11
AD0EN = 1
Idle
TC TC TC TC
Track T C T C T C T C
Idle
Track
T C T C T C..
T C T C T C..
T = Tracking
C = Converting
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4
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Rev. 1.1