C8051F50X Datasheet, PDF (71/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
SFR Definition 6.13. ADC0MX: ADC0 Channel Select
Bit
7
6
5
4
3
2
1
0
Name
ADC0MX[5:0]
Type
R
R
R/W
Reset
0
0
1
1
1
1
1
1
SFR Address = 0xBB; SFR Page = 0x00;
Bit Name
Function
7:6 Unused Read = 00b; Write = Don’t Care.
5:0 AMX0P[5:0] _{AMUX0 Positive Input Selection.}
000000:
000001:
000010:
000011:
000100:
000101:
000110:
000111:
001000:
001001:
001010:
001011:
001100:
001101:
001110:
001111:
010000:
010001:
010010:
010011:
010100:
010101:
010110:
010111:
011000:
011001:
011010:
011011:
011100:
011101:
011110:
011111:
100000–101111:
110000:
110001:
110010–111111:
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1 (Only available on 48-pin and 40-pin package devices)
P3.2 (Only available on 48-pin and 40-pin package devices)
P3.3 (Only available on 48-pin and 40-pin package devices)
P3.4 (Only available on 48-pin and 40-pin package devices)
P3.5 (Only available on 48-pin and 40-pin package devices)
P3.6 (Only available on 48-pin and 40-pin package devices)
P3.7 (Only available on 48-pin and 40-pin package devices)
Reserved
Temp Sensor
V_DD
GND
Rev. 1.1
71