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C8051F50X Datasheet, PDF (20/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family | |||
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C8051F50x-F51x
2. Ordering Information
The following features are common to all devices in this family:
ï® 50 MHz system clock and 50 MIPS throughput (peak)
ï® 4352 bytes of RAM (256 internal bytes and 4096 XRAM bytes)
ï® SMBus/I2C, Enhanced SPI, Enhanced UART
ï® Four Timers
ï® Six Programmable Counter Array channels
ï® Internal 24 MHz oscillator that is accurate to within ±0.5% across operating temperature and voltage.
ï® Internal Voltage Regulator
ï® 12-bit, 200 ksps ADC
ï® Internal Voltage Reference and Temperature Sensor
ï® Two Analog Comparators
ï
Table 2.1 shows the feature that differentiate the devices in this family.
20
Rev. 1.1
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