C8051F50X Datasheet, PDF (42/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
Table 5.2. Global Electrical Characteristics (Continued)
–40 to +125 °C, 24 MHz system clock unless otherwise specified.
I_DD4
Parameter
I_DD Supply Sensitivity⁴
I_DD Frequency Sensitivity ^4,5
Conditions
Min
V_DD = 2.6 V, F = 200 kHz
—
V_DD = 2.6 V, F = 1.5 MHz
—
V_DD = 2.6 V, F = 25 MHz
—
V_DD = 2.6 V, F = 50 MHz
—
F = 25 MHz
—
F = 1 MHz
—
V_DD = 2.1V, F < 12.5 MHz, T = 25 °C —
V_DD = 2.1V, F > 12.5 MHz, T = 25 °C —
V_DD = 2.6V, F < 12.5 MHz, T = 25 °C —
V_DD = 2.6V, F > 12.5 MHz, T = 25 °C —
Typ
130
990
14
25
68
73
0.46
0.36
0.64
0.47
Max Units
—
µA
—
µA
21
mA
33
mA
—
%/V
—
%/V
— mA/MHz
— mA/MHz
— mA/MHz
— mA/MHz
Notes:
1. Given in Table 5.4 on page 46.
2. V_IO should not be lower than the V_DD voltage.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Based on device characterization data; Not production tested. Does not include oscillator supply current.
5. IDD can be estimated for frequencies < 12.5 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate I_DD for >12.5 MHz, the
estimate should be the current at 50 MHz minus the difference in current indicated by the frequency
sensitivity number. For example: V_DD = 2.6 V; F = 20 MHz, I_DD = 26 mA - (50 MHz -
20 MHz) * 0.48 mA/MHz = 11.6 mA.
6. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by the
frequency sensitivity number for that range. When using these numbers to estimate Idle I_DD for >1 MHz, the
estimate should be the current at 50 MHz minus the difference in current indicated by the frequency
sensitivity number. 
For example: V_DD = 2.6 V; F = 5 MHz, Idle I_DD = 21 mA – (50 MHz – 5 MHz) x 0.41 mA/MHz = 2.6 mA.
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Rev. 1.1