C8051F50X Datasheet, PDF (125/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
SFR Definition 14.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
Name
EMAT ECAN0
Type
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
SFR Address = 0xE7; SFR Page = All Pages
Bit Name
Function
7:3 Unused Read = 00000b; Write = Don’t Care.
2 EMAT Enable Port Match Interrupt.
This bit sets the masking of the Port Match interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match
1 ECAN0 Enable CAN0 Interrupts.
This bit sets the masking of the CAN0 interrupt.
0: Disable all CAN0 interrupts.
1: Enable interrupt requests generated by CAN0.
0 EREG0 Enable Voltage Regulator Dropout Interrupt.
This bit sets the masking of the Voltage Regulator Dropout interrupt.
0: Disable the Voltage Regulator Dropout interrupt.
1: Enable the Voltage Regulator Dropout interrupt.
0
EREG0
R/W
0
Rev. 1.1
125