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C8051F50X Datasheet, PDF (164/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family
C8051F50x-F51x
Table 18.3. AC Parameters for External Memory Interface
Parameter
Description
Min*
TACS
TACW
TACH
Address/Control Setup Time
Address/Control Pulse Width
Address/Control Hold Time
0
1 x TSYSCLK
0
TALEH
Address Latch Enable High Time
1 x TSYSCLK
TALEL
Address Latch Enable Low Time
1 x TSYSCLK
TWDS
TWDH
TRDS
TRDH
Write Data Setup Time
Write Data Hold Time
Read Data Setup Time
Read Data Hold Time
1 x TSYSCLK
0
20
0
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Max*
3 x TSYSCLK
16 x TSYSCLK
3 x TSYSCLK
4 x TSYSCLK
4 x TSYSCLK
19 x TSYSCLK
3 x TSYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
164
Rev. 1.1