C8051F50X Datasheet, PDF (103/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

SFRPAGE
pushed to
SFRNEXT
SFR Page 0xC
Automatically
pushed on stack in
SFRPAGE on CAN0
interrupt
0xC
(CAN0)
0x0
(SPI0DAT)
C8051F50x-F51x
SFRPAGE
SFRNEXT
SFRLAST
Figure 13.3. SFR Page Stack After CAN0 Interrupt Occurs
While in the CAN0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the CAN0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to
access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that
was in the SFRPAGE register before the PCA interrupt (SFR Page 0x0C for CAN0) is pushed down the
stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in
this case SFR Page 0x00 for SPI0DAT) is pushed down to the SFRLAST register, the “bottom” of the
stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be
overwritten. See Figure 13.4.
Rev. 1.1
103