C8051F50X Datasheet, PDF (116/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
SMB0CF
0xC1
SMBus0 Configuration
SMB0CN
0xC0
SMBus0 Control
SMB0DAT
0xC2
SMBus0 Data
SMOD0
0xA9
UART0 Mode
SN0 - SN3 0xF9 - 0xFC Serial Number Registers
SP
0x81
Stack Pointer
SPI0CFG
0xA1
SPI0 Configuration
SPI0CKR
0xA2
SPI0 Clock Rate Control
SPI0CN
0xF8
SPI0 Control
SPI0DAT
0xA3
SPI0 Data
TCON
0x88
Timer/Counter Control
TH0
0x8C
Timer/Counter 0 High
TH1
0x8D
Timer/Counter 1 High
TL0
0x8A
Timer/Counter 0 Low
TL1
0x8B
Timer/Counter 1 Low
TMOD
0x89
Timer/Counter Mode
TMR2CN
0xC8
Timer/Counter 2 Control
TMR2H
0xCD
Timer/Counter 2 High
TMR2L
0xCC
Timer/Counter 2 Low
TMR2RLH
0xCB
Timer/Counter 2 Reload High
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
TMR3CN
0x91
Timer/Counter 3 Control
TMR3H
0x95
Timer/Counter 3 High
TMR3L
0x94
Timer/Counter 3 Low
TMR3RLH
0x93
Timer/Counter 3 Reload High
TMR3RLL
0x92
Timer/Counter 3 Reload Low
VDM0CN
XBR0
0xFF
0xE1
V_DD Monitor Control
Port I/O Crossbar Control 0
XBR1
0xE2
Port I/O Crossbar Control 1
XBR2
0xC7
Port I/O Crossbar Control 2
Page
232
234
236
249
96
94
259
261
260
261
271
274
274
273
273
272
278
280
280
279
279
284
286
286
285
285
144
184
185
186
Note: The CAN registers are not explicitly defined in this datasheet. See Table 22.2 on page 223 for the list of all
available CAN registers.
116
Rev. 1.1