C8051F50X Datasheet, PDF (225/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
SFR Definition 22.1. CAN0CFG: CAN Clock Configuration
Bit
7
6
5
4
3
2
1
0
Name Unused Unused Unused Unused Unused Unused
SYSDIV[1:0]
Type
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x92; SFR Page = 0x0C
Bit Name
Function
7:2 Unused Read = 000000b; Write = Don’t Care.
1:0 SYSDIV[1:0] CAN System Clock Divider Bits.
The CAN controller clock is derived from the CIP-51 system clock. The CAN control-
ler clock must be less than or equal to 25 MHz.
00: CAN controller clock = System Clock/1.
01: CAN controller clock = System Clock/2.
10: CAN controller clock = System Clock/4.
11: CAN controller clock = System Clock/8.
Rev. 1.1
225