C8051F50X Datasheet, PDF (186/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 1
Bit
7
6
5
Name ^{WEAKPUD XBARE}
Type
R/W
R/W
R/W
Reset
0
0
0
4
3
2
Reserved
R/W
R/W
R
0
0
0
1
0
LIN0E
R/W
R/W
0
0
SFR Address = 0xC7; SFR Page = 0x0F
Bit
Name
Function
7 WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6
XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5:1 Reserved Always Write to 00000b.
0
LIN0E LIN I/O Output Enable.
0: LIN I/O unavailable at Port pin.
1: LIN_TX, LIN_RX routed to Port pins.
186
Rev. 1.1