C8051F50X Datasheet, PDF (223/312 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x-F51x
22.2.4. CAN Register Assignment
The standard Bosch CAN registers are mapped to SFR space as shown below and their full definitions are
available in the CAN User’s Guide. The name shown in the Name column matches what is provided in the
CAN User's Guide. One additional SFR which is not a standard Bosch CAN register, CAN0CFG, is pro-
vided to configure the CAN clock. All CAN registers are located on SFR Page 0x0C.
Table 22.2. Standard CAN Registers and Reset Values
CAN
Addr.
Name
SFR Name SFR SFR Name SFR
(High)
Addr.
(Low)
Addr.
16-bit
SFR
Reset
Value
0x00 CAN Control Register
—
—
CAN0CN 0xC0
—
0x01
0x02
0x04
0x06
0x08
Status Register
Error Counter¹
Bit Timing Register²
Interrupt Register¹
0x0A Test Register
0x0C BRP Extension Register²
—
CAN0ERRH
CAN0BTH
CAN0IIDH
—
—
—
0x97
0x9B
0x9D
—
—
CAN0STAT
CAN0ERRL
CAN0BTL
CAN0IIDL
CAN0TST
CAN0BRPE
0x94
0x96
0x9A
0x9C
0x9E
0xA1
—
CAN0ERR
CAN0BT
CAN0IID
—
—
0x00
0x0000
0x2301
0x0000
0x00^3,4
0x00
0x10 IF1 Command Request CAN0IF1CRH 0xBF CAN0IF1CRL 0xBE CAN0IF1CR 0x0001
0x12 IF1 Command Mask
CAN0IF1CMH 0xC3 CAN0IF1CML 0xC2 CAN0IF1CM 0x0000
0x14 IF1 Mask 1
CAN0IF1M1H 0xC5 CAN0IF1M1L 0xC4 CAN0IF1M1 0xFFFF
0x16 IF1 Mask 2
CAN0IF1M2H 0xC7 CAN0IF1M2L 0xC6 CAN0IF1M2 0xFFFF
0x18 IF1 Arbitration 1
CAN0IF1A1H 0xCB CAN0IF1A1L 0xCA CAN0IF1A1 0x0000
0x1A IF1 Arbitration 2
CAN0IF1A2H 0xCD CAN0IF1A2L 0xCC CAN0IF1A2 0x0000
0x1C IF1 Message Control
CAN0IF1MCH 0xD3 CAN0IF1MCL 0xD2 CAN0IF1MC 0x0000
0x1E IF1 Data A 1
CAN0IF1DA1H 0xD5 CAN0IF1DA1L 0xD4 CAN0IF1DA1 0x0000
0x20 IF1 Data A 2
CAN0IF1DA2H 0xD7 CAN0IF1DA2L 0xD6 CAN0IF1DA2 0x0000
0x22 IF1 Data B 1
CAN0IF1DB1H 0xDB CAN0IF1DB1L 0xDA CAN0IF1DB1 0x0000
0x24 IF1 Data B 2
CAN0IF1DB2H 0xDD CAN0IF1DB2L 0xDC CAN0IF1DB2 0x0000
0x40 IF2 Command Request CAN0IF2CRH 0xDF CAN0IF2CRL 0xDE CAN0IF2CR 0x0001
0x42 IF2 Command Mask
CAN0IF2CMH 0xE3 CAN0IF2CML 0xE2 CAN0IF2CM 0x0000
0x44 IF2 Mask 1
CAN0IF2M1H 0xEB CAN0IF2M1L 0xEA CAN0IF2M1 0xFFFF
0x46 IF2 Mask 2
CAN0IF2M2H 0xED CAN0IF2M2L 0xEC CAN0IF2M2 0xFFFF
0x48 IF2 Arbitration 1
CAN0IF2A1H 0xEF CAN0IF2A1L 0xEE CAN0IF2A1 0x0000
0x4A IF2 Arbitration 2
CAN0IF2A2H 0xF3 CAN0IF2A2L 0xF2 CAN0IF2A2 0x0000
0x4C IF2 Message Control
CAN0IF2MCH 0xCF CAN0IF2MCL 0xCE CAN0IF2MC 0x0000
0x4E IF2 Data A 1
CAN0IF2DA1H 0xF7 CAN0IF2DA1L 0xF6 CAN0IF2DA1 0x0000
Notes:
1. Read-only register.
2. Write-enabled by CCE.
3. The reset value of CAN0TST could also be r0000000b, where r signifies the value of the CAN RX pin.
4. Write-enabled by Test.
Rev. 1.1
223