C8051F336 Datasheet, PDF (91/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
Interrupt Source
Table 15.1. Interrupt Summary
Interrupt Priority
Vector Order
Pending Flag
Enable Priority
Flag Control
Reset
External Interrupt 0
(/INT0)
Timer 0 Overflow
External Interrupt 1
(/INT1)
Timer 1 Overflow
UART0
Timer 2 Overflow
0x0000 Top
0x0003 0
0x000B 1
0x0013 2
0x001B 3
0x0023 4
0x002B 5
SPI0
0x0033 6
SMB0
Port Match
ADC0 Window
Compare
ADC0 Conversion
Complete
Programmable
Counter Array
Comparator0
RESERVED
Timer 3 Overflow
0x003B 7
0x0043 8
0x004B 9
0x0053 10
0x005B 11
0x0063 12
0x006B 13
0x0073 14
None
N/A
N/A
Always
Enabled
Always
Highest
IE0 (TCON.1)
Y Y EX0 (IE.0) PX0 (IP.0)
TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
IE1 (TCON.3)
Y Y EX1 (IE.2) PX1 (IP.2)
TF1 (TCON.7)
Y Y ET1 (IE.3) PT1 (IP.3)
RI0 (SCON0.0)
TI0 (SCON0.1)
Y N ES0 (IE.4) PS0 (IP.4)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
Y
N ET2 (IE.5) PT2 (IP.5)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
Y
N
ESPI0
(IE.6)
PSPI0
(IP.6)
RXOVRN (SPI0CN.4)
SI (SMB0CN.0)
Y
N
ESMB0 PSMB0
(EIE1.0) (EIP1.0)
None
N/A
N/A
EMAT
(EIE1.1)
PMAT
(EIP1.1)
AD0WINT
(ADC0CN.3)
Y
N
EWADC0 PWADC0
(EIE1.2) (EIP1.2)
AD0INT (ADC0CN.5) Y
N
EADC0 PADC0
(EIE1.3) (EIP1.3)
CF (PCA0CN.7)
CCFn (PCA0CN.n) Y
COVF (PCA0PWM.6)
N
EPCA0 PPCA0
(EIE1.4) (EIP1.4)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
N
N
ECP0
PCP0
(EIE1.5) (EIP1.5)
N/A
N/A N/A N/A
N/A
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N
N
ET3
PT3
(EIE1.7) (EIP1.7)
15.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Rev. 0.2
91