C8051F336 Datasheet, PDF (136/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
20.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A
software controlled value stored in the PnMATCH registers specifies the expected or normal logic values of
P0 and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the
software controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or
P1 input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Definition 20.3. P0MASK: Port 0 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
P0MASK[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xFE
Bit
Name
Function
7:0 P0MASK[7:0] Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
SFR Definition 20.4. P0MAT: Port 0 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P0MAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xFD
Bit
Name
Function
7:0 P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MAT which are set to ‘1’.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
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