C8051F336 Datasheet, PDF (20/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
Px.x
Px.x
Comparator 0
+
-
C0RSEF
VDD
Supply
Monitor
+
-
Enable
Power On
Reset
'0'
(wired-OR)
/RST
XTAL1
XTAL2
Low
Frequency
Oscillator
Internal
Oscillator
External
Oscillator
Drive
Missing
Clock
Detector
(one-
shot)
EN
PCA
WDT
EN
Reset
Funnel
(Software Reset)
SWRSF
Errant
FLASH
Operation
System
Clock
Clock Select
CIP-51
Microcontroller ^{System Reset}
Core
Extended Interrupt
Handler
Figure 1.3. On-Chip Clock and Reset
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 16 kB of Flash. This memory may be reprogrammed in-system in 512 byte
sectors, and requires no special off-chip programming voltage. See Figure 1.4 for the MCU system mem-
ory map.
20
Rev. 0.2