C8051F336 Datasheet, PDF (143/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
SFR Definition 20.16. P2MDIN: Port 2 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P2MDIN[7:0]
Type
R
R
R
R
R/W
Reset
0
0
0
0
1
1
1
1
SFR Address = 0xF3
Bit
Name
Function
7:4 UNUSED Unused. Read = 0000b; Write = Don’t Care
3:0 P2MDIN[3:0] Analog Configuration Bits for P2.3–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
SFR Definition 20.17. P2MDOUT: Port 2 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P2MDOUT[4:0]
Type
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA6
Bit
Name
Function
7:5 UNUSED Unused. Read = 000b; Write = Don’t Care
4:0 P2MDOUT[4:0] Output Configuration Bits for P2.4–P2.0 (respectively).
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
Rev. 0.2
143