C8051F336 Datasheet, PDF (45/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See Section “24. Timers” on page 187 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “20. Port
Input/Output” on page 126 for details on Port I/O configuration.
7.2.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to
be accurate. The minimum tracking time is given in Table 6.8. The AD0TM bit in register ADC0CN controls
the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a
conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold
mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-
conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode,
ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see
Figure 7.2). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep
modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due
to the settling time requirements described in Section “7.2.3. Settling Time Requirements” on page 47.
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