C8051F336 Datasheet, PDF (25/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
1.8. Comparator
C8051F336/7/8/9 devices include an on-chip voltage comparator that is enabled/disabled and configured
via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two compar-
ator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous)
output. Comparator response time is programmable, allowing the user to select between high-speed and
low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.9 shows the Comparator0 block diagram.
CPT0MX
CPT0CN
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P2.0
P2.2
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
P2.1
P2.3
VDD
CP0 +
CP0 -
CPT0MD
+
-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
Reset
Decision
Tree
CP0
Crossbar
CP0A
0
CP0RIF
1
0
CP0FIF
1
CP0EN
EA
0
1
CP0
0 Interrupt
1
Figure 1.9. Comparator0 Block Diagram
Rev. 0.2
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