C8051F336 Datasheet, PDF (28/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F336/7/8/9
Name
V_DD
GND
RST/
Pin
‘F336/7
3
2
4
Pin
‘F338/9
4
3
5
Type
Description
Power Supply Voltage.
Ground.
Note: This ground connection is required. The center pad may
optionally be connected to ground also.
D I/O
Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
C2CK
P2.0/
5
D I/O Clock signal for the C2 Debug Interface.
D I/O Port 2.0.
C2D
P2.4/
D I/O Bi-directional data signal for the C2 Debug Interface.
6
D I/O Port 2.4.
C2D
P0.0/
1
D I/O Bi-directional data signal for the C2 Debug Interface.
2
D I/O or Port 0.0.
A In
VREF
P0.1
20
A In External VREF input.
1
D I/O or Port 0.1.
A In
IDA0
P0.2/
19
AOut IDA0 Output.
24 D I/O or Port 0.2.
A In
XTAL1
P0.3/
18
A In External Clock Input. This pin is the external oscillator
return for a crystal or resonator.
23 D I/O or Port 0.3.
A In
XTAL2
P0.4
17
A I/O or External Clock Output. For an external crystal or resonator,
D In this pin is the excitation driver. This pin is the external clock
input for CMOS, capacitor, or RC oscillator configurations.
22 D I/O or Port 0.4.
A In
28
Rev. 0.2