C8051F336 Datasheet, PDF (23/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
1.5. Serial Ports
The C8051F336/7/8/9 Family includes an SMBus/I²C interface, a full-duplex UART with enhanced baud
rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hard-
ware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.6. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three program-
mable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in a variety of modes: Edge-Triggered Cap-
ture, Software Timer, High Speed Output, Pulse Width Modulator (8, 9, 10, 11, or 16-bit), or Frequency
Output. Additionally, Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a
system reset, Module 2 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O
and External Clock Input may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Digital Crossbar
Port I/O
Figure 1.7. PCA Block Diagram
Rev. 0.2
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