C8051F336 Datasheet, PDF (193/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
SFR Definition 24.2. TCON: Timer Control
Bit
7
6
5
4
3
2
1
0
Name ^TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Type ^R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x88; Bit-Addressable
Bit Name
Function
7
TF1 Timer 1 Overflow Flag.
Set to ‘1’ by hardware when Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6
TR1 Timer 1 Run Control.
Timer 1 is enabled by setting this bit to ‘1’.
5
TF0 Timer 0 Overflow Flag.
Set to ‘1’ by hardware when Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4
TR0 Timer 0 Run Control.
Timer 0 is enabled by setting this bit to ‘1’.
3
IE1
External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2
IT1
Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive.
/INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 15.5).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
1
IE0
External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by software but is automatically cleared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
0
IT0
Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be edge or level sensitive.
/INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 15.5).
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
Rev. 0.2
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