C8051F336 Datasheet, PDF (33/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

5. QFN-24 Package Specifications
C8051F336/7/8/9
Figure 5.1. QFN-24 Package Drawing
Table 5.1. QFN-24 Package Dimensions
Dimension Min
Typ
Max
Dimension Min
Typ
Max
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
4.00 BSC.
D2
2.60
2.70
2.80
e
0.50 BSC.
E
4.00 BSC.
E2
2.60
2.70
2.80
L
0.35
0.40
0.45
L1
0.00
—
0.15
aaa
—
—
0.15
bbb
—
—
0.10
ccc
—
—
0.05
ddd
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small
Body Components.
Rev. 0.2
33