C8051F336 Datasheet, PDF (88/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
Table 14.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
REF0CN
0xD1
Voltage Reference Control
RSTSRC
0xEF
Reset Source Configuration/Status
SBUF0
0x99
UART0 Data Buffer
SCON0
0x98
UART0 Control
SMB0ADM
0xE7
SMBus Slave Address Mask
SMB0ADR
0xD7
SMBus Slave Address
SMB0CF
0xC1
SMBus Configuration
SMB0CN
0xC0
SMBus Control
SMB0DAT
0xC2
SMBus Data
SP
0x81
Stack Pointer
SPI0CFG
0xA1
SPI Configuration
SPI0CKR
0xA2
SPI Clock Rate Control
SPI0CN
0xF8
SPI Control
SPI0DAT
0xA3
SPI Data
TCON
0x88
Timer/Counter Control
TH0
0x8C
Timer/Counter 0 High
TH1
0x8D
Timer/Counter 1 High
TL0
0x8A
Timer/Counter 0 Low
TL1
0x8B
Timer/Counter 1 Low
TMOD
0x89
Timer/Counter Mode
TMR2CN
0xC8
Timer/Counter 2 Control
TMR2H
0xCD
Timer/Counter 2 High
TMR2L
0xCC
Timer/Counter 2 Low
TMR2RLH
0xCB
Timer/Counter 2 Reload High
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
TMR3CN
0x91
Timer/Counter 3Control
TMR3H
0x95
Timer/Counter 3 High
TMR3L
0x94
Timer/Counter 3Low
TMR3RLH
0x93
Timer/Counter 3 Reload High
TMR3RLL
VDM0CN
XBR0
0x92
0xFF
0xE1
Timer/Counter 3 Reload Low
V_DD Monitor Control
Port I/O Crossbar Control 0
XBR1
0xE2
Port I/O Crossbar Control 1
Page
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115
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156
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157
79
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201
201
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113
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135
88
Rev. 0.2