C8051F336 Datasheet, PDF (22/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
1.4. Programmable Digital I/O and Crossbar
C8051F338/9 devices include 21 I/O pins (two byte-wide Ports and one 5-bit-wide Port). C8051F336/7
devices include 17 I/O pins (two byte-wide Ports and one 5-bit-wide Port). The C8051F336/7/8/9 Ports
behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog
input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-
drain output. The “weak pullups” that are fixed on typical 8051 devices may be globally disabled, providing
power saving capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See Figure 1.5.)
On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the
controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This
allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the
particular application.
XBR0, XBR1,
PnSKIP Registers
PnMDOUT,
PnMDIN Registers
Priority
Decoder
Highest
Priority
Lowest
Priority
2
UART
4
SPI
2
SMBus
CP0
2
Outputs
SYSCLK
PCA
4
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
4
P2 _(P2.0-P2.3*)
8
P0
I/O
Cells
Digital
8
P1
Crossbar
I/O
Cells
4
P2
I/O
Cells
*P2.1-P2.3 only available on
QFN24 Packages
Figure 1.5. Digital Crossbar Diagram
P0.0
P0.7
P1.0
P1.7
P2.0
P2.3*
22
Rev. 0.2