C8051F336 Datasheet, PDF (65/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
11. Comparator0
C8051F336/7/8/9 devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 11.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “20.4. Port I/O Initialization” on page 133). Comparator0 may also be used as a reset source (see
Section “18.5. Comparator0 Reset” on page 114).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“11.1. Comparator Multiplexer” on page 70.
CPT0CN
VDD
Comparator
Input Mux
CP0 +
+
CP0 -
-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
CPT0MD
Reset
Decision
Tree
CP0
Crossbar
CP0A
0
CP0RIF
1
0
CP0FIF
1
CP0EN
EA
0
1
CP0
0 Interrupt
1
Figure 11.1. Comparator0 Functional Block Diagram
Rev. 0.2
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