C8051F336 Datasheet, PDF (156/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
SFR Definition 21.3. SMB0ADR: SMBus Slave Address
Bit
7
6
5
4
3
2
1
0
Name
SLV[6:0]
GC
Type
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD7
Bit
Name
Function
7:1 SLV[6:0] SMBus Hardware Slave Address.
Defines the SMBus Slave Address(es) for automatic hardware acknowledgement.
Only address bits which have a ‘1’ in the corresponding bit position in SLVM[6:0]
are checked against the incoming address. This allows multiple addresses to be
recognized.
0
GC
General Call Address Enable.
When hardware address recognition is enabled (EHACK = 1), this bit will deter-
mine whether the General Call Address (0x00) is also recognized by hardware.
0: General Call Address is ignored.
1: General Call Address is recognized.
SFR Definition 21.4. SMB0ADM: SMBus Slave Address Mask
Bit
7
6
5
4
3
2
1
0
Name
SLVM[6:0]
EHACK
Type
R/W
R/W
Reset
1
1
1
1
1
1
1
0
SFR Address = 0xE7
Bit
Name
Function
7:1 SLVM[6:0] SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to ‘1’ in SLVM[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to ‘0’ are ignored (can be
either ‘0’ or ‘1’ in the incoming address).
0
EHACK Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
156
Rev. 0.2