C8051F336 Datasheet, PDF (46/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
CNVSTR
(AD0CM[2:0]=100)
SAR Clocks
A. ADC0 Timing for External Trigger Source
1 2 3 4 5 6 7 8 9 10 11 12 13 14
AD0TM=1
Low Power
or Convert
Track
Convert
Low Power
Mode
AD0TM=0
Track or Convert
Convert
Track
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
SAR
Clocks
AD0TM=1
B. ADC0 Timing for Internal Trigger Source
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Low Power
or Convert
Track
Convert
Low Power Mode
SAR
Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14
AD0TM=0
Track or
Convert
Convert
Track
Figure 7.2. 10-Bit ADC Track and Conversion Example Timing
46
Rev. 0.2