C8051F336 Datasheet, PDF (127/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
XBR0, XBR1,
PnSKIP Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
Lowest
Priority
2
UART
4
SPI
2
SMBus
CP0
2
Outputs
SYSCLK
PCA
4
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
4
P2 _(P2.0-P2.3*)
Priority
Decoder
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN Registers
Digital
Crossbar
8
P0
I/O
Cells
8
P1
I/O
Cells
4
P2
I/O
Cell
P0.0
P0.7
P1.0
P1.7
P2.0
P2.3*
To Analog Peripherals
(ADC0, CP0, VREF, XTAL)
*P2.1-P2.3 only available
on QFN24 Packages
Figure 20.1. Port I/O Functional Block Diagram
20.1. Port I/O Modes of Operation
Port pins P0.0 - P2.3 use the Port I/O cell shown in Figure 20.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a
high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = ‘1’).
20.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, VREF, or IDAC output
should be configured for analog I/O (PnMDIN.n = ‘1’). When a pin is configured for analog I/O, its weak pul-
lup, digital driver, and digital receiver are disabled. Port pins configured for analog I/O will always read
back a value of ‘0’.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
Rev. 0.2
127