C8051F336 Datasheet, PDF (37/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
Table 6.4. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max Units
RST Output Low Voltage
I_OL = 8.5 mA,
V_DD = 2.7 V to 3.6 V
—
—
0.6
V
RST Input Low Voltage
—
—
0.6
RST Input Pullup Current
RST = 0.0 V
—
50
100
µA
V_DD POR Threshold (V_RST)
2.40
2.55
2.70
V
Missing Clock Detector Time- Time from last system clock
out
rising edge to reset initiation
100
220
600
µs
Reset Time Delay
Delay between release of any
reset source and code
—
—
40
µs
execution at location 0x0000
Minimum RST Low Time to
Generate a System Reset
15
—
—
µs
V_DD Monitor Turn-on Time
100
—
—
µs
V_DD Monitor Supply Current
—
20
40
µA
Table 6.5. Flash Electrical Characteristics
V_DD = 2.7 to 3.6 V; –40 to +85 ºC unless otherwise specified.
Parameter
Conditions
Min
Flash Size
16384^*
Endurance
20 k
Erase Cycle Time
25 MHz System Clock
10
Write Cycle Time
25 MHz System Clock
40
*Note: 512 bytes at addresses 0x3E00 to 0x3FFF are reserved.
Typ
—
100 k
15
55
Max
—
—
20
70
Units
bytes
Erase/Write
ms
µs
Rev. 0.2
37