C8051F336 Datasheet, PDF (132/234 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F336/7/8/9
P0
P1
P2
SF Signa ls VREF IDA x 1 x 2
CNVSTR
PIN I/O
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1² 2²
TX0
RX0
SCK
MISO
MOSI
NSS¹
SDA
SCL
CP0
CP0A
S YS CL K
CEX 0
CEX 1
CEX 2
ECI
T0
T1
0011000000000000000
P 0S KIP [0:7]
P 1S KIP [0:7]
P 2S KIP [0:3
SF Signals
P ort pin potentially available to peripheral
S pecial Func tion S ignals are not ass igned by the c ross bar.
W hen these s ignals are enabled, the Cross Bar m ust be
m anually c onfigured to s k ip their c orres ponding port pins .
Notes:
1. NSS is only pinned out in 4-wire S P I M ode
2. P ins P 2.1-P 2.4 only on QFN24 Pack age
Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
132
Rev. 0.2