SI5380 Datasheet, PDF (8/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Functional Description
3.2 External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low phase noise reference clock
for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in the figure
below. The Si5380 includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit
of reduced noise coupling from external sources. Refer to the Table 5.12 Crystal Specifications on page 32 for crystal specifications.
A crystal frequency of 54 MHz is required, with a total accuracy of ±100 ppm* recommended for best performance. The Si5380 includes
built-in XTAL load capacitors (C_L) of 8 pF, which are switched out of the circuit when using an external XO. The Si5380 Reference
Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. The
Si5380 can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between the external XTAL or
REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this mode. It is important to
note that when using the REFCLK option the close-in phase noise of the outputs is directly affected by the phase noise of the external
XO reference. Refer to the Table 5.3 Input Clock Specifications on page 23 for REFCLK requirements when using this mode.
Note: Including initial frequency tolerance and frequency variation over the full operating temperature range, voltage range, load condi-
tions, and aging.
Differential Connection
0.1 uf
nc ^X1
ncX2
2xCL
XA
0.1 uf
XB
OSC
0.1 uf
2xCL
Note: 2.5 Vpp diff max
Si5380
Single-ended XO Connection
nc ^X1
ncX2
Note: 2.0 Vpp_se max
2xCL
0.1 uf
XA
OSC
XO with Clipped Sine
Wave Output
0.1 uf ^XB
2xCL
Si5380
CMOS/XO
Output
Single-ended Connection
nc ^X1
ncX2
Note: 2.0 Vpp_se max
2xCL
R1
0.1 uf
XA
OSC
R2
0.1 uf
0.1 uf ^XB
2xCL
Si5380
Crystal Connection
X1
XA
XTAL
XB
X2
2xCL
OSC
2xCL
Si5380
Figure 3.4. XAXB Crystal Resonator and External Reference Clock Connection Options
3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN)
Four clock inputs are available to synchronize the DSPLL. The inputs are compatible with both single-ended and differential signals.
Input selection can be manual (pin or register controlled) or automatic with definable priorities.
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