SI5380 Datasheet, PDF (16/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

3.5.3 Output Terminations
The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure.
Si5380 Data Sheet
Functional Description
DC-coupled LVDS
VDDO = 3.3 V, 2.5 V
OUTx
OUTxb
50
100
50
Si5380
AC-coupled LVDS/LVPECL
VDDO = 3.3 V, 2.5 V, 1.8 V
OUTx
50
OUTxb
100
50
Si5380
Internally
self-biased
DC-coupled LVCMOS
VDDO = 3.3 V, 2.5 V, 1.8 V
50
OUTx
Rs
OUTxb
Si5380
50
Rs
3.3 V, 2.5 V, 1.8 V
LVCMOS
AC-coupled LVPECL / CML
VDDO = 3.3 V, 2.5 V
Si5380
OUTx
OUTxb
VDD – 1.3 V
50
50
50
50
AC-coupled HCSL
VDDO = 3.3 V, 2.5 V, 1.8 V
Si5380
OUTx
50
OUTxb
50
R1
R1
R2
R2
VDDRX
Standard
HCSL
Receiver
For VCM = 0.35 V
VDDRX
3.3 V
2.5 V
1.8 V
R1
442 Ω
332 Ω
243 Ω
R2
56.2 Ω
59 Ω
63.4 Ω
Figure 3.14. Supported Output Terminations
3.5.4 Differential Output Modes
There are two selectable differential output modes: Normal and Low Power. Each output can support a unique mode.
• Differential Normal Mode: When an output driver is configured in normal amplitude mode, its output amplitude is selectable as one
of 8 settings ranging from 130 mVpp_se to 920 mVpp_se in increments of 100 mV. The output impedance in the normal mode is
100 Ω differential. Any of the ac-coupled terminations shown in Figure 3.14 Supported Output Terminations on page 15 are suppor-
ted in this mode.
• Differential Low Power Mode: When an output driver is configured in low power mode, its output amplitude is configurable as one
of 8 settings ranging from 200 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode
and supports standard 50 Ω PCB traces. Any of the ac-coupling terminations shown in Figure 3.14 Supported Output Terminations
on page 15 are supported in this mode.
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