SI5380 Datasheet, PDF(39/50 Page) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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SI5380 Datasheet, PDF (39/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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9. Pin Description

Si5380 Data Sheet

Pin Description

IN1 1

IN1b 2

IN_SEL0 3

IN_SEL1 4

PDNb 5

RSTb 6

X1 7

XA 8

XB 9

X2 10

OEb 11

INTRb 12

VDDA 13

IN2 14

IN2b 15

SCLK 16

GND

Pad

48 SYNCb

47 LOLb

46 VDD

45 OUT6

44 OUT6b

43 VDDO6

42 OUT5

41 OUT5b

40 VDDO5

39 I2C_SEL

38 OUT4

37 OUT4b

36 VDDO4

35 OUT3

34 OUT3b

33 VDDO3

Pin Name

IN0

IN0b

IN1

IN1b

IN2

IN2b

Figure 9.1. Si5380 64-QFN Top View

Table 9.1. Pin Descriptions

Pin Number

Pin Type1

Function

Crystal Input. Input pin for external crystal

(XTAL). Alternatively these pins can be driven with

an external reference clock (REFCLK). An internal

fault is XTAL mode. Single-ended inputs must be

connected to the XA pin, with the XB pin appropri-

ately terminated.

XTAL Shield. Connect these pins directly to the

crystal ground pins. Both the X1/X2 pins and Crys-

tal ground pins should be separated from the PCB

ground plane. Refer to the Reference Manual for

layout guidelines.

Clock Inputs. These pins accept an input clock

for synchronizing the device. They support both

differential and single-ended clock signals. Refer

to section 3.3.1 Input Configuration and Termina-

tions for input termination options. These pins are

high-impedance and must be terminated external-

ly, when being used. The negative side of the dif-

ferential input must be ac-grounded when accept-

ing a single-ended clock. Unused inputs may be

left unconnected.

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