SI5380 Datasheet, PDF (25/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
REFCLK⁴
f_{IN_REF}
LTE
—
54
—
MHz
Total Frequency Tolerance⁵
f_range
–100
—
+100
ppm
Input Voltage Swing
V_{IN_SE}
365
—
2000 mVpp_se
V_{IN_DIFF}
365
—
2500 mVpp_diff
Slew Rate^{1 , 2}
SR
Imposed for phase noise perform-
400
—
ance
—
V/µs
Input Duty Cycle
DC
40
—
60
%
Note:
1. Imposed for phase noise performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 – 0.2) * V_{IN_Vpp_se}) / SR.
3. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled, having a duty cycle
significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since the input thresholds
(VIL, VIH) of the input buffer are non-standard, refer to the input attenuator circuit for dc-coupled Pulsed LVCMOS in the in the
Si5380 Reference Manual . Otherwise, for standard LVCMOS input clocks, use the "AC-coupled Single-Ended" mode as shown
in Figure 6.14.
4. The REFCLK frequency for the Si5380 is fixed at 54 MHz. Contact the applications group for more information.
5. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), V_DD variation, load pulling, and aging.
Table 5.4. Control Input Pin Specifications¹
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si5380 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, PDNb, A1/SDO, SDA/SDIO, SCLK, A0/CSb)
Input Voltage Thresholds
V_IL
—
—
0.3xV_DDIO*
V
V_IH
0.7 x
—
—
V
V_DDIO*
Input Capacitance
C_IN
—
2
—
pF
Input Resistance
I_L
—
20
—
kΩ
Minimum Pulse Width
PW
RSTb, SYNCb, PDNb
100
—
—
ns
Note:
1. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD. See the Si5380 Reference Manual for more details
on the register settings.
Parameter
Output Frequency
Duty Cycle
Table 5.5. Differential Clock Output Specifications
Symbol
Test Condition
Min
Typ
f_OUT
0.48
—
DC
f < 400 MHz
48
—
400 MHz < f < 800 MHz
45
—
f >800 MHz
40
—
Max
1474.56
52
55
60
Unit
MHz
%
%
%
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