SI5380 Datasheet, PDF(30/50 Page) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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SI5380 Datasheet, PDF (30/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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Si5380 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Maximum Phase Transient

tSWITCH

Automatic Hitless Switch

2.8

Pull-in Range

Î©P

500

ppm

Input-to-Output Delay Variation

tIODELAY

In Regular Mode

tZDELAY

In Zero Delay Mode2

110

RMS Jitter Generation5

JGEN

LVPECL Output

@ 1474.56 MHz

0.070 0.080 ps RMS

LVPECL Output

0.080 0.125 ps RMS

@ 122.88 MHz

Phase Noise Performance5

(122.88 MHz Carrier Frequency)

10Hz

100 Hz

1 kHz

â71

dBc/Hz

â98

dBc/Hz

â123

dBc/Hz

10 kHz

â136

dBc/Hz

100 kHz

â144

dBc/Hz

1 MHz

â154

dBc/Hz

10 MHz

â165

dBc/Hz

Spur Performance 5(122.88 MHz Carri-

SPUR

Up to 1 MHz offset

â103

dBc

er Frequency)

From 1 MHz to 30 MHz offset

â95

dBc

Note:

1. Measured as time from valid VDD/VDDA rails (both >90% of settled voltage) to when the serial interface is ready to respond to

commands.

2. Measured from the INx input to the feedback input, with both clocks running at 15.36 MHz and having the same slew rate. The

rise time of the reference input should not exceed 200 ps in order to guarantee this specification.

3. Actual loop bandwidth might be lower; refer to ClockBuilder Pro for actual value on your frequency plan.

4. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock

time was measured with nominal and fastlock bandwidths both set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively,

using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first

rising edge of the clock reference and the LOL indicator de-assertion.

5. Jitter generation test conditions: fIN = 30.72 MHz, fOUT = 122.88 MHz LVPECL, DSPLL LBW = 100 Hz. Does not include jitter

from PLL input reference.

Parameter

SCL Clock Frequency

SMBus Timeout

Hold Time (Repeated)

START Condition

Low Period of the SCL

Clock

Table 5.9. I2C Timing Specifications (SCL,SDA)

Symbol

Test Condition

fSCL

tHD:STA

tLOW

When Timeout is Enabled

Min

Max Min Max Unit

Standard Mode

Fast Mode

100 kbps

400 kbps

100

400

kHz

4.0

0.6

Âµs

4.7

1.3

Âµs

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