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SI5380 Datasheet, PDF (2/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator | |||
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1. Feature List
The Si5380 highlighted features are listed below.
⢠Digital frequency synthesis eliminates external VCXO and an-
alog loop filter components
⢠Supports JESD204B clocking: DCLK and SYSREF
⢠Input frequency range:
⢠Differential: 10 MHz â 750 MHz
⢠LVCMOS: 10 MHz â 250 MHz
⢠Output frequency range:
⢠Differential: up to 1.47456 GHz
⢠LVCMOS: up to 250 MHz
⢠Excellent jitter performance:
⢠70 fs typ (12 kHz â 20 MHz)
⢠Phase noise floor: â159 dBc/Hz
⢠Spur performance: â103 dBc max (relative to a 122.88 MHz
carrier)
⢠Configurable outputs:
⢠Signal swing: 200 to 3200 mVpp
⢠Compatible with LVDS, LVPECL
⢠LVCMOS 3.3, 2.5, or 1.8 V
⢠Output-output skew: 20 ps (typical, same N-divider)
⢠Adjustable output-output delay: 68 ps/step, ±128 steps
Si5380 Data Sheet
Feature List
⢠Optional Zero Delay mode
⢠Independent output supply pins: 3.3, 2.5, or 1.8 V
⢠Core voltage:
⢠VDD = 1.8 V ±5%
⢠VDDA = 3.3 V ±5%
⢠Automatic free-run, lock, and holdover modes
⢠Digitally selectable loop bandwidth: 0.1 Hz to 4 kHz
⢠Hitless input clock switching
⢠Status monitoring (LOS, OOF, LOL)
⢠Serial interface: I2C or SPI In-circuit programmable with non-
volatile OTP memory
⢠ClockBuilderTM Pro software tool simplifies device configura-
tion
⢠4 input, 12 output, 64QFN
⢠Temperature range: â40 to +85 °C
⢠Pb-free, RoHS-6 compliant
silabs.com | Smart. Connected. Energy-friendly.
Rev. 0.96 | 1
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