SI5380 Datasheet, PDF (17/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Functional Description
3.5.5 Programmable Common Mode Voltage for Differential Outputs
The common mode voltage (VCM) for the differential normal and low power modes is programmable in 100 mV increments from 0.7 V
to 2.3 V depending on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the
output drivers.
3.5.6 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled with source-side series termination as shown in the figure below.
DC-coupled LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
OUTx
Rs
OUTxb
3.3 V, 2.5 V, 1.8 V
LVCMOS
50
50
Rs
Figure 3.15. LVCMOS Output Terminations
3.5.7 LVCMOS Output Impedance and Drive Strength Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-
ble output impedance selections for each VDDO options as shown in the table below.
Table 3.3. LVCMOS Output Impedance and Drive Strength Selections
VDDO
OUTx_CMOS_DRV
Source Impedance (Zs)
Drive Strength (Iol/Ioh)
3.3 V
0x01
38 Ω
10 mA
0x02
30 Ω
12 mA
0x03*
22 Ω
17 mA
2.5 V
0x01
43 Ω
6 mA
0x02
35 Ω
8 mA
0x03*
24 Ω
11 mA
1.8 V
0x03*
31 Ω
5 mA
Note: Use of the lowest impedance setting is recommended for all supply voltages for best edge rates.
3.5.8 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. OUT0 and OUT0A share the same VDDO pin.
OUT9 and OUT9A also share the VDDO pin. All other outputs have their own individual VDDO pins. Each output driver automatically
detects the voltage on the VDDO pin to properly determine the correct output voltage.
3.5.9 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-
ble enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.
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