SI5380 Datasheet, PDF (42/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Pin Description
Pin Name
Pin Number
Pin Type¹
Function
IN_SEL0
3
IN_SEL1
4
I
Input Reference Select. ² The IN_SEL[1:0] pins
I
are used in manual pin controlled mode to select
the active clock input as shown in Table 3.2 Table
6.2 on page 8. These pins are internally pulled-
down and may be left unconnected when unused.
RSVD
25
Reserved. Leave disconnected.
Power
VDD
32
VDD
46
VDD
60
P
Core Supply Voltage. The device operates from
a 1.8 V supply. A 1 uF bypass capacitor should be
P
placed very close to each pin.
P
VDDA
13
P
Core Supply Voltage 3.3 V. This core supply pin
requires a 3.3 V power source. A 1 uF bypass ca-
pacitor should be placed very close to this pin.
VDDO0
22
VDDO1
26
VDDO2
29
VDDO3
33
VDDO4
36
VDDO5
40
VDDO6
43
P
Output Clock Supply Voltage. Supply voltage
(3.3 V, 2.5 V, 1.8 V) for OUTx, OUTxb Outputs.
P
Note that VDDO0 supplies power to OUT0 and
P
OUT0A; VDDO9 supplies power to OUT9 and
OUT9A. Leave VDDO pins of unused output driv-
P
ers unconnected. An alternative option is to con-
nect the VDDO pin to a power supply and disable
P
the output driver to minimize current consumption.
P
A 1 µF bypass capacitor should be placed very
close to each connected VDDO pin.
P
VDDO7
49
P
VDDO8
52
P
VDDO9
57
P
GND PAD
P
Ground Pad. This pad provides connection to
ground and must be connected for proper opera-
tion.
Note:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
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