SI5380 Datasheet, PDF (26/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Parameter
Symbol
Test Condition
Min
Output-Output Skew
T_SK
Differential Outputs
—
Same N-divider
Differential Outputs
—
Different N-dividers
OUT-OUTb Skew
T_{SK_OUT}
Measured from the positive to
—
negative output pins
Output Voltage Ampli- Normal Mode
tude¹
V_OUT
V_DDO =
LVDS
340
3.3 V or
LVPECL
530
2.5 V or
1.8 V
Low Power Mode
V_OUT
V_DDO =
LVDS
300
3.3 V or
2.5 V or
1.8 V
V_DDO = 3.3 V
LVPECL
530
or 2.5 V
Common Mode Volt-
age^{1, 2}
Normal or Low Power Modes
V_CM
V_DDO =
3.3 V
LVDS
LVPECL
1.10
1.90
V_DDO =
2.5 V
LVPECL
LVDS
1.15
V_DDO =
LVDS
0.87
1.8 V
Rise and Fall Times
t_R/t_F
Normal Mode
—
(20% to 80%)
Low Power Mode
—
Differential Output Im-
Z_O
Normal Power Mode
—
pedance³
Low Power Mode
—
Si5380 Data Sheet
Electrical Specifications
Typ
Max
Unit
20
50
ps
20
100
ps
0
100
ps
470
550
mVpp_se
810
950
420
530
mVpp_se
820
1060
1.25
1.30
V
2.05
2.10
1.25
1.30
0.93
0.98
170
240
ps
300
430
100
—
Ω
Hi-Z
—
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