SI5380 Datasheet, PDF (15/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Functional Description
3.4.7 Interrupt Pin INTRb
An interrupt pin INTRb indicates a change in state of the status indicators shown in the figure below. Any of the status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the
interrupt. The sticky version of the fault monitors is used for this function to ensure that the fault condition is still available when re-
sponding to the interrupt.
LOS_FLG[3-0]
OOF_FLG[3-0]
LOL_FLG
LOS_INTR_MSK[3-0]
OOF_INTR_MSK[3-0]
LOL_INTR_MSK
HOLD_FLG
HOLD_INTR_MSK
CAL_FLG
CAL_INTR_MSK
SYSINCAL_FLG
LOSXAXB_FLG
LOSREF_FLG
XAXB_ERR_FLG
SMBUS_TIMEOUT_FLG
SYSINCAL_INTR_MSK
LOSXAXB_INTR_MSK
LOSREF_INTR_MSK
XAXB_ERR_INTR_MSK
SMB_TMOUT_INTR_MSK
Figure 3.13. Interrupt Triggers and Masks
INTRb
3.5 Outputs
The Si5380 supports 12 differential output drivers which can be independently configured as differential or LVCMOS.
3.5.1 Output Crosspoint
The output crosspoint allows any of the N dividers to connect to any of the clock outputs.
3.5.2 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable covering a wide variety of signal formats in-
cluding LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as
LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended
outputs.
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