SI5380 Datasheet, PDF (31/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Parameter
HIGH Period of the SCL
Clock
Set-up Time for a Repea-
ted START Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA
and SCL Signals
Fall Time of Both SDA and
SCL Signals
Set-up Time for STOP
Condition
Bus Free Time between a
STOP and START Condi-
tion
Data Valid Time
Data Valid Acknowledge
Time
Symbol
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_r
t_f
t_SU:STO
t_BUF
t_VD:DAT
t_VD:ACK
Test Condition
Si5380 Data Sheet
Electrical Specifications
Min
Max Min Max Unit
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
100
—
100
—
ns
250
—
100
—
ns
—
1000
20
300
ns
—
300
—
300
ns
4.0
—
0.6
—
µs
4.7
—
1.3
—
µs
—
3.45
—
0.9
µs
—
3.45
—
0.9
µs
Figure 5.1. I²C Serial Prot Timing Standard and Fast Modes
Parameter
SCLK Frequency
SCLK Duty Cycle
Table 5.10. SPI Timing Specifications (4-Wire)
Symbol
Min
Typ
f_SPI
—
—
T_DC
40
—
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Max
20
60
Unit
MHz
%
Rev. 0.96 | 30