SI5380 Datasheet, PDF (32/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Parameter
SCLK Rise and Fall Time
SCLK Period
Delay Time, SCLK Fall to SDO
Active
Delay Time, SCLK Fall to SDO
Delay Time, CSb Rise to SDO
Tri-State
Setup Time, CSb to SCLK
Hold Time, SCLK Fall to CSb
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects
(CSb)
TSU1
SCLK
CSb
SDI
SDO
Symbol
Tr/Tf
T_C
T_D1
T_D2
T_D3
T_SU1
T_H1
T_SU2
T_H2
T_CS
TD1
Min
Typ
—
—
50
—
—
—
—
—
—
—
25
—
25
—
12.5
—
12.5
—
1.9
—
TSU2
TH2
TD2
Si5380 Data Sheet
Electrical Specifications
Max
Unit
10
ns
—
ns
12.5
ns
12.5
ns
12.5
ns
—
ns
—
ns
—
ns
—
ns
—
T_c
TC
TH1
TCS
TD3
Figure 5.2. 4-Wire SPI Serial Interface Timing
Table 5.11. SPI Timing Specifications (3-Wire)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Rise and Fall Time
SCLK Period
Delay Time, SCLK Fall to SDIO Turn-on
Delay Time, SCLK Fall to SDIO Next-bit
Delay Time, CSb Rise to SDIO Tri-State
Setup Time, CSb to SCLK
Hold Time, SCLK Fall to CSb
Symbol
f_SPI
T_DC
Tr/Tf
T_C
T_D1
T_D2
T_D3
T_SU1
T_H1
Min
Typ
—
—
40
—
—
—
50
—
—
—
—
—
—
—
25
—
25
—
Max
20
60
10
—
12.5
12.5
12.5
—
—
Unit
MHz
%
ns
ns
ns
ns
ns
ns
ns
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